Co-located with HiPEAC'24
18th January 2024
Co-located with HiPEAC'24
18th January 2024
Co-located with HiPEAC'24
18th January 2024
Co-located with HiPEAC'24
18th January 2024
To keep up pace with an exponentially growing amount of sensor data and enable more intelligent, accurate, safe, and timely interactions with the surrounding environment, next-generation edge devices will need to run AI algorithms and compute intense tasks with very low latency (i.e., units of ms or less) and using ultra-low energy (i.e., tens of mW or less). This can only be achieved by combining innovations at all levels of electronics design hierarchy in a holistic way: from high-level algorithms and low-level software compilation to architecture design, RTL synthesis, and down to physical layout implementation. A major source of inspiration to guide these innovations are energy-efficient sensing and processing mechanisms in eyes and brains.
NeuroEdge workshop aims to bring together neuroscientists, researchers, engineers, innovators, entrepreneurs, and businesses to exchange ideas and share their latest results and findings. A major objective of NeuroEdge is thus to provide a venue to discuss how edge technology should evolve to support advanced AI-based concepts, which cannot be efficiently implemented using existing technology, and ultimately enable strong business opportunities. The workshop topics include, but are not limited to:
Electronic paper submission requires a full paper, up to 8 double-column pages in ACM format, including figures and references.
Papers should be submitted in PDF format though the EasyChair website (link button below).
Papers presented in NeuroEdge will be invited to submit an extended version for consideration for publication in a special issue of an ACM journal (TBD).
Paper Submission Deadline: November 26th, 2023 - CLOSED
Notification of Acceptance: December 12th, 2023
Camera-Ready Papers: January 6th, 2024
Workshop: January 18th, 2024
Xabier Iturbe received his MSc degree in Electrical, Electronics and Communications Engineering from the University of the Basque Country (Spain) in 2007, and his PhD in Electronics Engineering from the University of Edinburgh (UK) in 2013. He is a senior research engineer at IKERLAN (Spain), where he coordinates the centre’s research activities in neuromorphic and AI hardware design, with a focus on applicability to industry customers. He also coordinates the Horizon Europe research project NimbleAI (nimbleai.eu), the SiliconBurmuin initiative in the Basque Country (bmh.gaia.es/neuromorphic), and the neuromorphic and AI technologies working group of the Spanish Association of Semiconductor Industry (aesemi.org/en/commissions). In 2014, he received a Marie Curie Fellowship to conduct research at NASA’s Jet Propulsion Laboratory (USA) and Arm (UK), exploring techniques to enhance fault-tolerance in Arm Cortex-R CPUs and make them suitable for space use. From 2016 to 2018 Xabier was the Arm University Program EMEA manager, driving the company's technology outreach to the academic community and pre-competitive research organizations in the EMEA region to enable Arm-based education, research, and entrepreneurship. He has co-authored over 40 journal and conference papers and has 9 granted patents.
Henk Corporaal is Professor in Embedded System Architectures at the Eindhoven University of Technology (TU/e) in The Netherlands. He has gained a MSc in Theoretical Physics from the University of Groningen, and a PhD in Electrical Engineering, in the area of Computer Architecture, from Delft University of Technology. His research is on low power multi-processor, heterogenous processing architectures, their programmability, and the predictable design of soft- and hard real-time systems. This includes research and design of embedded system architectures, including CGRAs, SIMD, VLIW and GPUs, on accelerators, the exploitation of all kinds of parallelism, fault-tolerance, approximate computing, architectures for machine and deep learning, optimizations and mapping of deep learning networks, and the (semi-)automated mapping of applications to these architectures. Corporaal has co-authored over 500 journal and conference papers. Furthermore he invented a new class of VLIW architectures, the Transport Triggered Architectures, which is used in several commercial products, and by many research groups. He initatiated and leads the Dutch NWO perspectief program on Efficient Deep Learning (efficientdeeplearning.nl); in this program many research institutes and over 30 companies participate. He also is the PI of the EU project CONVOLVE (convolve.eu) on seamless design of smart edge processors. For further details see corporaal.org.
Irem Boycat is a Research Scientist at IBM Research Europe, Zurich, Switzerland. She received her PhD degree in Electrical Engineering from Ecole Polytechnique Federale de Lausanne (EPFL), Switzerland, in 2020. Previously, she had obtained an M.Sc. degree in Electrical Engineering from EPFL, Switzerland, in 2015, and a B.Sc. degree in Electronics Engineering from Sabanci University, Turkey, in 2013. Her research is primarily centered around analog in-memory computing for accelerating deep neural networks using phase-change memory devices. She has co-authored over 50 scientific papers in journals and conferences, received four best conference presentation/paper/poster awards and holds 8 granted patents. She was a co-recipient of the 2018 IBM Pat Goldberg Memorial Best Paper Award and 2020 EPFL PhD Thesis Distinction in Electrical Engineering.
Matěj Hejda has received his MSc. in Nanotechnology from Technical University of Liberec (Czechia) while undertaking his Master's project in the Optoelectronics (Prof Pruneri) group at ICFO (Spain). In 2023, he has obtained his Ph.D. from the Institute of Photonics at University of Strathclyde (Glasgow, UK), where he was working in Dr Antonio Hurtado’s group, focusing on neuromorphic information processing using lasers and optoelectronic systems as functional primitives towards more efficient, light-enabled computing. In 2023, he has joined the EU-based team of the Large-Scale Integrated Photonics (LSIP) group in Hewlett Packard Enterprise (Belgium), where he currently works as an Architecture & System Design Research Scientist. His main research is in optical computing architectures - in particular, he is focusing on integrated photonic architectures for AI acceleration, exploring practical use-cases in such accelerators, and investigating spike-based photonic computing. His other interests include neuro-inspired information processing, hardware-software co-design, silicon photonics and unconventional/analog computing.
Arne Erdmann studied physics at the University of Kiel and joined Raytrix in 2011. Moving from R&D to technology transfers, he now serves as Raytrix‘s CBDO.
Anders Mikkelsen graduated from Åarhus University in 2001. He then moved to Lund University and is now Professor and director of the Swedish Strategic Research Area NanoLund which encompasses more than 450 researchers and graduate students. His research deals with nanostructures/device imaging and function to the atomic scale combined with advanced lasers, synchrotron sources, and nanophotonic components as well as surface and interface material science of nanostructures. The aim is a better fundamental understanding of complex, dynamic condensed matter systems, as well as developing novel materials and devices for next-generation computing, energy systems, and products to improve our lives. He has authored ~190 peer-reviewed journal articles and has given more than 60 invited talks at conferences, workshops, and institutes. He has been awarded a wide range of grants as main PI including from ERC and EIC, totaling ~9MEuro since 2010, and is elected fellow of the American Vacuum Society (AVS). Presently, he is the coordinator of the EIC pathfinder project InsectNeuroNano which aims to develop nanophotonic on-chip devices for integrated sensing and neural computation, inspired by the insect brain.
Hamid Tabani received his Ph.D. degree with the mark of excellent Cum Laude from Universitat Politècnica de Catalunya (UPC). His area of expertise is Computer Architecture, Autonomous Driving and Real-time systems. His research in the past decade is published in top-tier conferences and journals such as HPCA, PACT, DAC, DATE, SAC, ICCD, ECRTS, RTAS, and IEEE Micro, and received multiple awards. He is currently working as a senior computer architect at GrAI Matter Labs developing the next generation of AI processors. Dr. Tabani is a HiPEAC member.
Bastian Weiß graduated in mathematics at JKU Linz (Austria). After some years as a (embedded) software engineer, he is now working on low-latency neural networks for embedded systems. As Senior Software Developer at Viewpointsystem, Vienna, Bastian focuses on the development of energy-efficient, high-performance eye-tracking sensors for smart glasses, such as in augmented and virtual reality applications. Bastian’s research interests include the robustness of image processing techniques in real-life scenarios and data protection.include the robustness of image processing techniques in real-life scenarios and data protection.
Peter Priller graduated in electrical engineering at the TU Graz (Austria). After some years in semiconductor design focusing on RFID in ASIC development, he moved on to AVL Graz, working in various positions from software development to system architecture / real-time systems to software project management. He is now at AVL ITS global Research and Technology management, where he serves as Principal Technology Scout for embedded systems. Research interests include safety, reliability and security in cyber-physical systems, wired and wireless networking systems in automotive applications, and embedded AI merging with IoT. He is also a guest lecturer at TU Graz.
Marian Verhelst's research interests are in embedded machine learning, computer architectures and hardware accelerators for AI, and low-power sensing and processing for perceptive systems. Marian is currently a professor at the Electrical Engineering department of KU Leuven (Belgium). Previously, from 2008 till 2011, she worked as a research scientist in the Radio Integration Research Lab of Intel Labs, Hillsboro OR, and in 2005 she was a visiting scholar at the Berkeley Wireless Research Center(BWRC) of UC Berkeley. Marian holds a prestigious ERC Starting Grant from the European Union on embedded Bayesian reasoning. She is a member of the DATE conference executive committee and was a member of the ESSCIRC and ISSCC TPCs and of the ISSCC executive committee. Marian is an IEEE SSCS Distinguished Lecturer, a member of the Young Academy of Belgium, an associate editor for TCAS-II and JSSC, and a member of the STEM advisory committee to the Flemish Government.
Tobias Grosser is a reader (associate professor) in the School of Informatics at the University of Edinburgh and a member of the Edinburgh Compiler and Architecture Design Group. He is most widely known for his work on polyhedral loop optimization in production compilers such as GCC (graphite) and LLVM (Polly) during his masters at University of Passau (Germany) with Christian Lengauer and later his Ph.D. as a Google Fellow at Ecole Normale Supérieure Paris (France) Albert Cohen. As Ambizione Fellow at ETH Zurich Tobias expanded his research towards high-performance linear programming solvers, domain-specific compilers (e.g., for climate science), and open-source software for hardware design. Today, Tobias is interested in bringing open-source production compiler technology to a wide range of domains (e.g., databases, SMT solvers, formal theorem provers) and is in particular interested in identifying new ideas that cross domain boundaries.
Simon Davidson received a BEng(Hons) in Electronic Engineering from the University of Sheffield in 1989 and completed a PhD from the same university in 1999. In 1990 he became a research assistant in the Electronic Engineering department at Sheffield, working on a number of ESPRIT-funded integrated circuit design projects. In 1993, he joined SGS-Thomson (formerly INMOS) in Bristol (UK) to contribute to the CHAMELEON Project - a 64-bit superscalar microprocessor aimed at MPEG decoding and multimedia applications - where he was part of the core processor pipeline design team, creating pipeline micro-architecture for an out-of-order superscalar pipeline. In 1996, he joined Hewlett-Packard's Integrated Circuit Business Division (ICBD) in Grenoble (France), working with customers in several European design centers on the backend design (place-and-route and layout) of a range of chips for HP peripherals. Early in 2000, he joined ARC International - a configurable microprocessor IP design company in north London - as a principal engineer in the core processor group. Notable roles included technical lead for the development of their new dense instruction set - ARCompact - and co-technical lead on their deeper pipeline processor line, beginning with the ARC700. After a time at The University of York, David moved in 2009 to The University of Manchester to join the SpiNNaker project and its follow-up project - BIMPA - to develop neural architectures for a massively parallel SpiNNaker machine.
NeuroEdge is co-located with HiPEAC'24 conference at the Science Congress Center Munich (SCCM), which is halfway between Munich and the international airport. The closest underground station (U-Bahn) Garching-Forschungszentrum is right next to the entrance of the SCCM.
NeuroEdge @ HiPEAC'24 Conference